1. Field
The present embodiment relates to a semiconductor device and a system using a semiconductor device.
2. Description of the Related Art
There has been developed a memory LSI having a data compression test function built therein which combines data in the inside of the memory LSI and performs a read/write test.
A test technique for a semiconductor device is disclosed in, for example, Japanese Laid-open Patent Publication No. 2004-251730, Japanese Laid-open Patent Publication No. 2004-21833, and Japanese Laid-open Patent Publication No. 2002-82714. In Japanese Laid-open Patent Publication No. 2004-251730, there is disclosed a technique of enhancing a self-test function performed by a BIST (Built-In Self Test) circuit and realizing a reduction in a chip size or a reduction in the number of external pins in the semiconductor device. In Japanese Laid-open Patent Publication No. 2004-21833, there is disclosed a technique of realizing a reduction in a test cost by enabling to perform a self test on a peripheral function block in the semiconductor device. In Japanese Laid-open Patent Publication No. 2002-82714, there is disclosed a self-diagnosing circuit of an input/output circuit system capable of rapidly and easily detecting a spot where an electrical defect is generated.